The invention relates to semiconductor device fabrication, particularly to dielectric materials, and more particularly to spacers for gate electrodes.
Integrated circuits (ICs) typically comprise many complementary metal oxide semiconductor (CMOS) field effect transistors (FETs). FETs typically comprise gate structures (or, simply “gates”) disposed between drain and source regions. The drain and source regions are typically located within a semiconductor film or substrate. The gates are provided on a top surface of the film or substrate, and there is a gate dielectric layer, typically oxide, underneath the gate. The drain and source regions can be heavily doped with a P-type dopant (e.g., boron) or an N-type dopant (e.g., phosphorous. Typically, a spacer isolates the gate from the metal contact with each of the diffusion (source/drain) regions of the transistor. The spacer is a dielectric material, typically oxide or nitride.
Typical sidewall spacers are formed using a conformal deposition of a spacer material over the gate structure, followed by a directional etch, as disclosed by Pogge in U.S. Pat. No. 4,256,514, “Method for Forming a Narrow Dimensioned Region on a Body,” assigned to International Business Machines, Inc. The directional etch removes all the spacer material from the horizontal surfaces, but leaves “spacers” at the sidewalls of the gates. These spacers are inherently self-aligned with the gate.
Silicon dioxide (SiO2, also referred to simply as “oxide”) has a dielectric constant k of at least 3.85, typically 4.1–4.3, or higher. Silicon nitride (Si3N4, also referred to simply as “nitride”, often abbreviated as “SiN”) has a dielectric constant k of approximately 7.0. A free space (e.g., air) has a dielectric constant k of approximately 1.0. By definition, a vacuum has a dielectric constant k of 1.0.
In many spacer applications silicon nitride is typically used to provide selectivity to the contact dielectric (e.g. silicon dioxide), in spite of its higher dielectric constant.
Low-k (or “low k”) dielectric materials are known, and are typically defined as materials having a dielectric constant k less than 3.85—in other words, less than oxide. Medium-k dielectric materials are also known and, as used herein, these materials have a dielectric constant k less than 7.0, or less than nitride, but greater than oxide. Collectively, low-k and medium-k materials are referred to herein as “reduced dielectric constant materials”.
A variety of low-k and medium-k materials are known. They can characterized by their composition and/or by the way in which they typically are deposited.
Deposition is a process whereby a film of either electrically insulating (dielectric) or electrically conductive material is deposited on the surface of a wafer. Chemical Vapor Deposition (CVD) is used to deposit both dielectric and conductive films via a chemical reaction that occurs between various gases in a reaction chamber. Plasma enhanced Chemical Vapor Deposition (PECVD) uses an inductively coupled plasma to generate different ionic and atomic species during the deposition process. PECVD typically results in a low temperature deposition compared to the corresponding thermal CVD process. Spin-on deposition (also called “spin coating”) is used to deposit materials such as photoresist. A wafer is coated with material in liquid form, then spun at speeds up to 6000 rpm, during which the liquid is uniformly distributed on the surface by centrifugal forces, followed by a low temperature bake which solidifies the material.
Low-k and Medium-k Materials
As used herein, a low-k material is a material which has a dielectric constant k less than 3.85 (less than oxide), and a medium-k material is a material which has a dielectric constant k less than 7.0 (nitride) and greater than 3.85.
Examples of spin-on low-k materials include:                BCB (divinylsiloxane bisbenzocyclobutene), sold by Dow Chemical.        SiLK™, an organic polymer with k=2.65, similar to BCB, sold by Dow Chemical.        NANOGLAS™, an inorganic porous polymer with k=2.2, sold by Honeywell.        FLARE 2.0™ dielectric, an organic low-k poly(arylene)ether available from Allied Signal, Advanced Microelectronic Materials, Sunnyvale, Calif.        inorganic materials such as spin-on glass (SOG), fluorinated silicon glass (FSG) and, particularly, methyl-doped porous silica which is referred to by practitioners of the art as black diamond, or BD. About 36% of a BD layers volume is in the form of pores having a diameter between about 8 and 24 Angstroms.        organo-silicate materials, such as JSR LKD 5109 (a spin-on material, Japan Synthetic Rubber).        organic polymers (fluorinated or non-fluorinated), inorganic polymers (nonporous), inorganic-organic hybrids, or porous materials (xerogels or aerogels).        materials in the parylene family of polymers, the polynapthalene family of polymers, or polytetrafluoroethylene.        
Examples of low-k Chemical Vapor Deposition (CVD) and Plasma Enhanced CVD (PECVD) low-k materials include:                Black Diamond™, a organosilicon glass (OSG) which is a Si—O—C—N type of material, with a dielectric constant k of 2.7 to 3.0 (e.g., 2.9), sold by Applied Materials Inc. Black Diamond™ comprises about 12% carbon and about 9% nitrogen.        CORAL™, also an organosilicon glass OSG) which is a Si—O—C—H type of material, with k of 2.7–3.0, sold by Novellus Systems, Inc. CORAL™ comprises about 30% carbon.        fluorinated SiO2 glass, and amorphous C:F.        
Examples of medium-k CVD materials include:                FSG (fluorinated silicon glass) with k value of 3.4. Composition (Si—O—F).        TERA™, a silicon carbide (Si—C—H) type of material with k=5 developed by IBM.        Blok™, a silicon carbide (Si—C—H) type material with k=5 sold by AMAT Corp.        
Porositylt is known that pores in dielectric materials can lower the dielectric constant. Low-k and medium-k dielectric materials can typically be deposited ab initio either with or without pores, depending on process conditions. Since air has a near 1 dielectric constant, porous films exhibit reduced dielectric constants than the base material in which they are developed. Generally, it is the spin-on materials (e.g., SILK, NANOGLASS) materials that exhibit a high degree of porosity. The PECVD materials generally do not exhibit such high degree of porosity, due to the method of deposition. As a result it is very difficult to prepare a CVD film with a k value <2.5.
Examples of dielectric materials which may be formed ab-initio having pores include:                organic materials, such as porous SiLK (tm, Dow).        inorganic materials, such as nanoglass (tm, Honeywell).        organo-silicate materials, such as JSR LKD 5109 (a spin-on material, Japan Synthetic Rubber).        
These materials have pores, usually (typically) ranging in size from 0.1 to 10 nanometers. The density of the pores, in other word how much of the material is pores versus the overall volume of the material, is typically approximately 20%–75% pores.
U.S. Pat. No. 6,383,951 discloses a low dielectric constant material for integrated circuit fabrication. A method is provided for forming a material with a low dielectric constant, suitable for electrical isolation in integrated circuits. The material and method of manufacture has particular use as an interlevel dielectric between metal lines in integrated circuits. In a disclosed embodiment, methylsilane is reacted with hydrogen peroxide to deposit a silicon hydroxide layer incorporating carbon. The layer is then treated by exposure to a plasma containing oxygen, and annealing the layer at a temperature of higher than about 450 degrees-C. or higher.
U.S. Pat. No. 6,194,748 ('748 patent) discloses a MOSFET with suppressed gate-edge fringing field effect. The transistor includes a low-k dielectric spacer and a high-k gate dielectric. The high-k gate dielectric can be tantalum pentaoxide or titanium dioxide. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs).
As shown in the '748 patent, a transistor 12 is disposed on a semiconductor substrate 14, such as, a single crystal silicon wafer. Transistor 12 is part of a portion 10 of an integrated circuit (IC) manufactured on a wafer (such as, a silicon wafer). Transistor 12 preferably has a gate length of less than 100 nanometer (nm) (e.g., approaching 50 um). The substrate 14 can be any semiconductor material, including gallium arsenide (GaAs), silicon (Si), germanium (Ge), or other material. Alternatively, substrate 14 can be a thin-film layer that is part of a silicon-on-insulator substrate. (1 micron=1e−6 meter=1000 nm=10000 Å)
Transistor 12 includes a gate stack or structure 18, a source region 22, and a drain region 24. Source region 22 and drain region 24 also include a source extension 23 and a drain extension 25, respectively. In the exemplary embodiment, source region 22 and drain region 24 have deep contact regions 17 and 19, respectively, which are 60–120 nm deep (60–120 nm below a top surface 39 of substrate 14).
Transistor 12 can be an N-channel or a P-channel field effect transistor (FET). Transistor 12 can be subject to two-dimensional channel-doping engineering and includes pocket or halo implant regions. Regions 22 and 24 can be planar, as shown in FIG. 1, or can be raised or elevated source and drain regions.
Transistor 12 can be substantially formed by conventional semiconductor processing techniques to form gate structure 18, including gate oxide or dielectric layer 34, source region 22, and drain region 24. Transistor 12 is provided between structures 58.
Extensions 23 and 25 are preferably ultra-shallow extensions (e.g., junction depth is less than 15–30 nm), which are thinner (i.e., shallower) than regions 17 and 19 of regions 22 and 24. Each of extensions 23 and 25 has a width of 40–80 nm (from left-to-right) and is integral with regions 22 and 24, respectively. Extensions 23 and 25 are disposed partially underneath a gate dielectric layer 34. Ultra-shallow extensions 23 and 25 help transistor 12 achieve substantial immunity to short-channel effects. Short-channel effects can degrade performance of transistor 12, as well as the manufacturability of the IC associated with transistor 12. Regions 22 and 24 and, hence, extensions 23 and 25, have a concentration of 1019 to 1020 dopants per cubic centimeter.
The transistor 12 includes a pair of low-k dielectric spacers (38). Low-k dielectric spacers (38) can be 1,000–2,000 Angstroms thick and 30–40 nm wide. Spacers 38 are preferably less than half of the width of extensions (23) and (25). The spacers (38) can be manufactured from a variety of low-k materials.
A silicide layer 70 is formed over drain region 24 and source region 22 of transistor 12. A portion 60 of silicide layer 70 is provided over source region 22, and a portion 62 of silicide layer 70 is provided over drain region 24. Portions 60 and 62 are preferably 100–200 Angstrom thick layers of titanium silicide (TiSi2), nickel silicide (NiSi2), cobalt silicide (CoSi2), or other conductive materials. Seventy percent (70–140 Angstrom) of portions 60 and 62 extend below top surface 39 of substrate 14.
In the '748 patent, the use of spacers 38 manufactured from low-k material advantageously reduces the gate-edge fringing capacitance associated at transistor 12 (especially transistor 12, which utilizes a high-k gate dielectric layer 34. Spacers 38 preferably have a k value of less than 2.0. The low-k material around the edges of gate structure 18 suppresses gate-edge fringing field effects so high-k gate dielectric layer 34 can be utilized with transistor 12. Thus, spacers 38 advantageously reduce overlap capacitance resulting from the gate-edge fringing electrical fields, thereby benefiting the speed of the transistor. Additionally, spacers 38 significantly improve sub-threshold voltage characteristics and low-voltage control of ultra-thin transistors, such as, transistor 12.
In the '748 patent, the low-k materials (k less than 3.0, preferably less than 2.0) can be created from vapor deposition and spin-on coating techniques. For example, vapor deposition of parylene and polynapthalene families of polymers and polytetrafluoroethylene (PTFE) can be utilized to form low-k materials. Alternatively, plasma enhanced chemical vapor deposition (PECVD), high density plasma CVD of fluorinated SiO2 glass, and amorphous C:F can form the low-k dielectric material. Air-gap formation and plasma polymerization of pentafluorostyrene and pulse plasma polymerization of PTFE can also be utilized. Additionally, materials can be deposited by spin coating; spin coating materials include organic polymers (fluorinated or non-fluorinated), inorganic polymers (nonporous), inorganic-organic hybrids, or porous materials (xerogels or aerogels).
In the application of reduced dielectric constant spacers, it is not generally possible to use porous materials ab initio due to attack of the underlying film in the pores. That is to say, the pores as deposited provide openings from which the plasma chemistry may attack the underlying material during the spacer reactive ion etch (RIE).